Conventionally, a voltage multiplying circuit has been known, which is constituted by capacitors and switches and is capable of generating an intermediate voltage between one and two times larger than a source voltage(see Japanese Laid-Open Patent Application no. 5-276737(published on Oct. 22, 1993)).
Referring to FIG. 6, the following explanation discusses the conventional voltage multiplying circuit.
As shown in FIG. 6, the voltage multiplying circuit is constituted by a smoothing capacitor 1, an electric charge supplying capacitor 2, switches 3 through 6, a constant voltage element 7, and a power source 8. The switching of the switches 3 through 6 is controlled by a first and second clock signals(not shown) so as to generate an intermediate voltage one to two times larger than the power source 8, and then, the intermediate voltage is outputted from an output terminal 9.
As shown in FIG. 6, between the power source 8 and the output terminal 9, the smoothing capacitor 1 is provided, and the constant voltage element 7, the switch 3, and the switch 6 are connected in series. Between the power source 8 and a connecting point of the switches 3 and 6, the switch 5 and the electric charge supplying capacitor 2 are connected in series. Between the ground and a connecting point P of the electrical charge supplying capacitor 2 and the switch 5, the switch 4 is provided.
The first and second clock signals are arranged so as to have opposite phases each other. The switches 3 and 4 are switched so as to be synchronous to the first clock signal; meanwhile, the switches 5 and 6 are switched so as to be synchronous to the second clock signal.
The following explanation discusses an operation of the voltage multiplying circuit which has the above-mentioned construction. Here, VDD represents voltage of the power source 8, and .DELTA.V represents a decrease in voltage of the constant voltage element 7.
When the switches 3 and 4 are closed in synchronization with the first clock signal, the power source 8, the constant voltage element 7, the switch 3, the electrical charge supplying capacitor 2, and the switch 4 form a closed circuit, so that the electric charge supplying capacitor 2 is charged with a voltage which is smaller than the voltage VDD by the voltage .DELTA.V(=VDD-.DELTA.V), which is a voltage drop of the constant voltage element 7.
And then, when the switches 3 and 4 are opened and the switches 5 and 6 are closed in synchronization with the second clock signal, the voltage VDD of the power source 8 is applied to the connecting point P so as to increase the voltage of the connecting point P by the voltage VDD. The voltage charged to the electric charge supplying capacitor 2 (VDD-.DELTA.V) is added to the voltage VDD of the connecting point P (=2VDD-.DELTA.V), and the added voltage is outputted as output voltage from the output terminal 9.
As described above, the voltage VDD of the power source 8 is doubled, is subtracted by a voltage drop of the constant voltage element 7, and is outputted from the output terminal 9. The constant voltage element 7 having a different rating is adopted so as to obtain a desired intermediate voltage which is one to two times the voltage VDD, in accordance with the constant voltage element 7.
Here, referring to FIGS. 7 and 8, the following explanation discusses another conventional voltage multiplying circuit which is constituted by capacitors and switches and which outputs a voltage which is twice the power source.
As shown in FIG. 7, a voltage multiplying circuit 20 is constituted by P channel MOSs 14 and 16, an N channel MOS 15, and a voltage multiplying capacitor C. The voltage multiplying circuit 20 is mainly composed of a voltage multiplying section 21 which doubles voltage, and inverter circuits 11 through 13 for controlling the voltage multiplying operation.
Both of the P channel MOS 14 and the N channel MOS 15 are pre-charging transistors. The output of the inverter circuit 12 is applied to the gate of the P channel MOS 14, and the power source voltage VEE is applied to the source of the P channel MOS 14. The output of the inverter circuit 11 is applied to the gate of the N channel MOS 15, and the source of the N channel MOS 15 is grounded. The voltage multiplying capacitor C is provided between the drains of the P channel MOS 14 and the N channel MOS 15.
An output terminal VOUT is extended from an electrode CAP.sub.+, which is one of the electrodes of the voltage multiplying capacitor C, to the outside. The other electrode CAP.sub.- is connected to the drain of the P channel MOS 16. The power source voltage VEE is applied to the source of the P channel MOS 16, and the output of the inverter circuit 13 is applied to the gate of the P channel MOS 16.
An input signal IN2 shown in FIG. 8 is applied to the inverter circuit 13. Further, an input signal IN1 shown in FIG. 8 is applied to the inverter circuit 11. Additionally, the inverter circuit 11 and the inverter circuit 12 are cascaded.
Referring to FIG. 8, the following explanation discusses an operation of the voltage multiplying circuit having the above-mentioned construction.
When the input signals IN1 and IN2, which belong to a low level in a binary level(hereinafter, simply referred to as a low level), are respectively applied to the inverter circuits 11 and 13, signals which belong to a high level in a binary level (hereinafter, simply referred to as a high level) are respectively applied to the gates of the N channel MOS 15 and the P channel MOS 16. At this time, a low-level signal is applied to the gate of the P channel MOS 14.
With this arrangement, the P channel MOS 16 is turned off; meanwhile, the P channel MOS 14 and the N channel MOS 15 are turned on. As a result, the voltage multiplying capacitor C is charged by the power source voltage VEE, so that the voltage across the voltage multiplying capacitor C becomes virtually equal to the power source voltage VEE(corresponding to a period indicated by 1 in FIG. 8).
And then, when the input signals IN1 and IN2 are changed from a low level to a high level, low-level signals are respectively applied to the gates of the N channel MOS 15 and the P channel MOS 16; meanwhile, a high-level signal is applied to the gate of the P channel MOS 14. With this arrangement, the P channel MOS 16 is turned on; meanwhile, the P channel MOS 14 and the N channel MOS 15 are turned off. At this time, the voltage of the electrode CAP.sub.- of the voltage multiplying capacitor C is increased from the ground level to the power source voltage VEE (see the wave of the signal CAP.sub.- in FIG. 8). As a result, (a) the power source voltage VEE charged during the period 1 is added to (b) the increase in voltage of the electrode CAP.sub.-, that is the power source voltage VEE applied in response to the turn-on of the P channel MOS 16, so as to obtain 2VEE voltage(see the wave of the signal CAP.sub.+ in FIG. 8) of the output terminal VOUT (corresponding to a period indicated by 3 in FIG. 8).
Moreover, with regard to the input signals IN2 and IN1, in order to prevent feedthrough current, a holding period is provided so as to prevent the input signals from being simultaneously changed from a low level to a high level, or from a high level to a low level (corresponding to periods 2 and 4 of FIG. 8).
Referring to FIG. 9, the following explanation discusses still another conventional voltage multiplying circuit which can triple voltage by using the voltage multiplying circuit shown in FIG. 7. Here, for convenience of explanation, those members that have the same functions and that are shown in FIG. 7 are indicated by the same reference numerals and the description thereof is omitted.
This voltage multiplying circuit is basically obtained by combining a pair of the voltage multiplying circuits shown in FIG. 7. Additionally, the inverter circuits are commonly used for controlling on/off of the respective MOSs.
The voltage multiplying circuit of FIG. 9 is mainly constituted by: a voltage multiplying circuit 20 which is provided with the voltage multiplying section 21 shown in FIG. 7 (for convenience of explanation, hereinafter, referred to as a first voltage multiplying section 21); a second voltage multiplying section 22 which has the same circuit construction as the first voltage multiplying section 21 and which triples voltage; and an outputting section 25 which is provided with a P channel MOS 23 and a smoothing capacitor 24.
From an output terminal VOUT of the voltage multiplying circuit 20 (for convenience of explanation, hereinafter, referred to as an output terminal VOUT 21), the output is applied to the source of the P channel MOS16 of the second voltage multiplying section 22. The gates of P channel MOSs 14 of the first and second voltage multiplying sections 21 and 22 are connected to each other. Moreover, the gates of N channel MOSs 15 of the first and second voltage multiplying sections 21 and 22 are connected to each other. The gates of P channel MOSs 16 of the first and second voltage multiplying sections 21 and 22 are connected to each other.
From an output terminal VOUT of the second voltage multiplying section 22 (for convenience of explanation, hereinafter, referred to as an output terminal VOUT 22), the output is applied to the source of the P channel MOS 23. The drain of the P channel MOS 23 is extended to the outside as an output terminal 25. The gate of the P channel MOS 23 is connected to the gate of the N channel MOS 16 of the second voltage multiplying section 22. Further, the smoothing capacitor 24 is provided between the output terminal VOUT 25 and the ground.
The following explanation briefly discusses an operation of the voltage multiplying circuit which triples voltage with the above-mentioned construction. Here, the operation performed in the voltage multiplying circuit 20 has been already discussed; therefore, the explanation thereof is omitted. The following explanation describes an operation performed after the output of the voltage multiplying circuit 20 (=2VEE) has been applied to the second voltage multiplying section 22.
When low-level input signals IN1 and IN2 are respectively applied to the inverter circuits 11 and 13, in the second voltage multiplying section 22, high level signals are applied to the gates of the N channel MOS 15 and the P channel MOS 16; meanwhile, a low level signal is applied to the gate of the P channel MOS 14.
With this arrangement, in the second voltage multiplying section 22, the P channel MOS 16 is turned off; meanwhile, the P channel MOS 14 and the N channel MOS 15 are turned on. As a result, the voltage multiplying capacitor C is charged by the power source voltage VEE, so that the voltage across the multiplying capacitor C becomes virtually equal to the power source voltage VEE.
And then, when the input signals IN1 and IN2 are changed from a low level to a high level, in the second voltage multiplying section 22, low level signals are respectively applied to the gates of the N channel MOS 15 and the P channel MOS 16; meanwhile, a high level signal is applied to the gate of the P channel MOS 14. With this arrangement, the P channel MOS 16 is turned on; meanwhile, the P channel MOS 14 and the N channel MOS 15 are turned off, so that the voltage of the output terminal VOUT 21 is applied to the electrode CAP.sub.- of the voltage multiplying capacitor C. As a result, the voltage of the electrode CAP.sub.- is increased from the ground level to the 2VEE voltage level. Therefore, the power source voltage VEE that has been charged is added to the increase in voltage of the electrode CAP.sub.-, that is the power source voltage 2VEE applied in response to the turn-on of the P channel MOS 16, so as to obtain a 3VEE voltage of the output terminal VOUT 25. With this arrangement, voltage which is triple of the power source voltage is outputted from the voltage multiplying circuit.
Additionally, in the first and second voltage multiplying sections 21 and 22, the voltage multiplying capacitor C and the smoothing capacitor 24 are externally installed.
However, the conventional arts has the following problems:
Specifically, with regard to the conventional switched-capacitor voltage multiplying circuits of FIGS. 6 and 7, one voltage multiplying circuit can realize an intermediate voltage which is larger than the power source voltage by between one and two times, and a voltage multiplication level which is two times as large as the power source voltage; however, it is not possible to achieve a plurality of multiplication levels by using one voltage multiplying circuit.
For instance, a liquid crystal driving driver of a liquid crystal driving device requires relatively large voltage values as compared with a power source voltage of a general-purpose LSI. Furthermore, each maker normally requires different voltage values for the system construction, etc.; therefore, in order to meet the needs, it has been conventionally necessary to develop a liquid crystal driving driver for each power source specification of the user, resulting in poor versatility that imposes a considerable inconvenience on the user.
Further, with regard to the conventional voltage multiplying circuit of FIG. 9, if the wiring is changed, it is possible to switch the multiplication level so as to double or triple the power source voltage and to output the multiplied voltage; however, in this case, it is necessary to change the construction including the circuit wiring and the connection of the voltage multiplying capacitor C.